The present invention relates to a semiconductor integrated circuit device composed of transistors of the insulating gate field effect type, and more specifically relates to the electrostatic damage protection structure of the transistors.
Referring to FIG. 22, a brief description is given for a typical construction of the conventional semiconductor integrated circuit device. The device 0 is composed of a peripheral connection area 2 for external connection and an internal circuit area 1 which performs certain logical processing and so on. These areas contain an integrated basic structural element composed of a metal-oxide-semiconductor transistor hereinafter, referred to as a "MOS transistor") of the field effect type. In order to facilitate understanding of the description, a MOS transistor belonging to the peripheral connection area 2 is specifically referred to as a peripheral transistor, and another MOS transistor belonging to the internal circuit area 1 is referred to as an internal transistor.
The peripheral connection area 2 is provided with input terminals 3, output terminals 4, a power supply terminal 5, a ground terminal 6 and so on. Generally, an input protection circuit 7 is interposed between the input terminal 3 and the internal circuit area 1. The output terminals 4 are clasified into two groups. One group is called a CMOS output terminal utilizing an inverter 8 composed of a pair of complementary MOS transistors or a CMOS transistor pair. The other group is called an open-drain output terminal utilizing an N channel MOS transistor 9 which is connected in an open-drain manner. The CMOS transistor and the N channel transistor are examples of a peripheral transistor. Aside from these terminals, the power supply terminal 5 is connected to a power line VDD, and the ground terminal 6 is connected to a ground line GND.
Next referring to FIG. 23, brief description is given for the typical structure of the MOS transistor. The illustrated transistor is an N channel MOS transistor having a conventional N.sup.+ single drain structure (hereinafter, referred to as a "CONV structure"). A gate electrode G is formed on a semiconductor substrate SUB composed of silicon through a gate insulating film OX composed of silicon dioxide. The substrate SUB is a P type substrate. The gate insulating film OX has a thickness on the order of 100-800 .ANG.. A pair comprised of source region S and drain region D are formed on opposite sides of the gate electrode G in the form of an N.sup.+ type impurity diffusion region. A channel region ch is defined between the pair of diffusion regions. The conductivity of the channel region ch is controlled by the gate electrode G.
Recently, the size of the transistor element has been considerably reduced in order to increase an integration density of the semiconductor integrated circuit device. Namely, the length of the channel region ch (hereinafter, referred to as "channel length") is continuously being made shorter and shorter. However, if the channel length is extremely shortened in the CONV structure, there is frequently caused characteristic degradation due to hot electron damage.
Referring to FIG. 24, a brief description is given for a modified MOS transistor having a lightly doped drain structure (hereinafter, referred to as "LDD structure"). This LDD structure was developed in order to prevent degradation of durability due to hot electron damage, which becomes serious with the miniaturization of the transistor element. As shown in the figure, the LDD structure is provided with a drain region D composed of an N.sup.- type impurity diffusion region and a contiguous N.sup.+ type impurity diffusion region. A source region S has the same contiguous diffusion region structure. According to a so-called scaling rule, the shorter the channel length, the thinner proportionally the thickness of the gate insulating film OX. For example, the thickness of the gate insulating film is about 300-400 .ANG. in the CONV structure, whereas the film thickness is reduced to 100-300 .ANG. in the micronized LDD structure. On the other hand, the CONV structure has a typical drain withstand voltage or breakdown voltage on the order of 10 V, whereas the LDD structure can be adopted to raise the drain withstand voltage to over 20 V.
Referring to FIG. 25, a concise description is given for the problem of the prior art to be solved by the invention. FIG. 25 is a graph showing the relation between the transistor breakdown voltage and the channel length (hereinafter, occasionally referred to as "L-length"). As shown in the graph, the gate insulation withstand voltage or gate breakdown voltage of the miniaturized LDD structure is lower than that of the CONV structure, because the thickness of the gate insulating film is reduced in the LDD structure according to the scaling rule, as compared to the CONV structure. On the other hand, the drain breakdown voltage or DC withstand voltage is significantly raised as compared to the CONV structure. Further, punch-through frequently occurs when the L-length is set below 3 .mu.m in the CONV structure so that the drain breakdown voltage falls below a given IC rated voltage, whereas a punch-through is not observed as long as the L-length is set over 1 .mu.m in the LDD structure.
As understood from the FIG. 25 graph, when the LDD structure is adopted to facilitate the miniaturization of the semiconductor device, there occurs an inversion phenomenon that the drain breakdown voltage exceeds the gate breakdown voltage. Consequently, there is caused the drawback that a resistance against electrostatic damage or destruction (hereinafter, referred to as "ESD resistance") of the MOS transistor is degradated adversely by the inversion phenomenon. Namely, when an external electrostatic stress is impressed on the drain electrode to flow a surge current, the stress is directly applied to the gate insulating film as the drain withstand voltage is raised by the LDD structure, thereby increasing a risk of the gate insulation destruction.
Referring back to FIG. 22, more detailed description is given for the drawback of the prior art. Conventionally, the internal transistors which constitute the internal circuit area 1 have substantially the same structure as the peripheral transistors which constitute the peripheral connection area 2 in view of the semiconductor fabrication process. In miniaturization of the semiconductor device, the first priority has been given to the improvement in durability against hot electron damage, while no practical countermeasure has been adopted with regard to the electrostatic damage. It is important for the internal transistor to prevent durability degradation due to hot electron damage or hot carrier damage in order to ensure operation reliability of the device. Further, reduction in the ESD resistance is not serious for the internal transistor because the same is not exposed directly to an external electrostatic stress. On the other hand, the peripheral transistor is directly affected by an external electrostatic stress, hence a poor ESD resistance would cause electrostatic destruction of the transistor to thereby disadvantageously generate defects. For example, the N channel MOS transistor 9 connected to the output terminal 4 of the open-drain type is particularly susceptible to electrostatic stress as compared to the output inverter 8 of the CMOS transistor pair, thereby causing serious problems.